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Dual D-Type Flip-Flop with Preset and Clear

General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption of standard CMOS inte grated circuits, along with the ability to drive 10 LS-TTL loa

Dual D-Type Flip-Flop with Preset and Clear

文件：392.39 Kbytes Page：11 Pages

Dual D-Type Flip-Flop with Preset and Clear

文件：382 Kbytes Page：11 Pages

封裝/外殼：14-DIP（0.300"，7.62mm） 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 包裝：管件 描述：IC FF D-TYPE DUAL 1BIT 14DIP 集成電路（IC） 觸發(fā)器

Dual D-Type Flip-Flop with Preset and Clear

General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption of standard CMOS inte grated circuits, along with the ability to drive 10 LS-TTL loa

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes Page：21 Pages

High Speed CMOS Logic

文件：467.12 Kbytes Page：6 Pages