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74HC74價(jià)格
參考價(jià)格：￥0.4785
型號(hào)：74HC74BQ,115 品牌：NXP 備注：這里有74HC74多少錢，2025年最近7天走勢(shì)，今日出價(jià)，今日競(jìng)價(jià)，74HC74批發(fā)/采購報(bào)價(jià)，74HC74行情走勢(shì)銷售排行榜，74HC74報(bào)價(jià)。| 型號(hào) | 功能描述 | 生產(chǎn)廠家 企業(yè) | LOGO | 操作 |
|---|---|---|---|---|
74HC74 | Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred | ONSEMI 安森美半導(dǎo)體 |   | |
74HC74 | Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops | Philips 飛利浦 | | |
74HC74 | Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | |
74HC74 | Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | |
74HC74 | High Speed CMOS Logic Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1μA Asynchronous Set-Reset Capability ±4mA Output Drive at 5V Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacement for obsolete components in long term programs | SS | | |
74HC74 | Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | | |
74HC74 | High Speed CMOS Logic 文件：467.12 Kbytes Page：6 Pages | SS | | |
74HC74 | High Speed CMOS Logic 文件：791.12 Kbytes Page：6 Pages | SS | | |
74HC74 | Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飛利浦 | | |
High Speed CMOS Logic Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1μA Asynchronous Set-Reset Capability ±4mA Output Drive at 5V Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacement for obsolete components in long term programs | SS | | ||
4-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES ? Synchronous or asynchronous operation ? 3-state outputs ? 30 MHz (typical) shift-in and shift-out rates ? Readily expandable in word | Philips 飛利浦 | | ||
4-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES ? Synchronous or asynchronous operation ? 3-state outputs ? 30 MHz (typical) shift-in and shift-out rates ? Readily expandable in word | Philips 飛利浦 | | ||
4-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES ? Synchronous or asynchronous operation ? 3-state outputs ? 30 MHz (typical) shift-in and shift-out rates ? Readily expandable in word | Philips 飛利浦 | | ||
5-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. | Philips 飛利浦 | | ||
5-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. | Philips 飛利浦 | | ||
5-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. | Philips 飛利浦 | | ||
Dual D-Type Flip Flop Preset and Clear Features ? High speed: fmax = 77 MHz (typ.) at VCC = 5 V ? Low power dissipation: ICC = 2 μA (max) at Ta = 25°C ? High noise immunity: VNIH = VNIL = 28 VCC (min) ? Output drive capability: 10 LSTTL loads ? Symmetrical output impedance: |IOH| = IOL = 4 mA (min) ? Balanced propagation delays: | TOSHIBA 東芝 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops | Philips 飛利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | | ||
CMOS Digital Integrated Circuits Silicon Monolithic Functional Description ? Dual D-Type Flip-Flop with Preset and Clear General The 74HC74D is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The sign | TOSHIBA 東芝 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | | |
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops | Philips 飛利浦 | | ||
Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred | ONSEMI 安森美半導(dǎo)體 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops | Philips 飛利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | | |
Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred | ONSEMI 安森美半導(dǎo)體 | | ||
Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred | ONSEMI 安森美半導(dǎo)體 | | ||
Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred | ONSEMI 安森美半導(dǎo)體 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops | Philips 飛利浦 | | ||
Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred | ONSEMI 安森美半導(dǎo)體 | | ||
Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred | ONSEMI 安森美半導(dǎo)體 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops | Philips 飛利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名廠家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops | Philips 飛利浦 | | ||
High Speed CMOS Logic 文件：791.12 Kbytes Page：6 Pages | SS | | ||
封裝/外殼：16-SOIC（0.295"，7.50mm 寬） 功能：異步，同步 包裝：托盤 描述：IC FIFO REGISTER 64X4 16SOIC 集成電路（IC） FIFO 存儲(chǔ)器 | ETC 知名廠家 | ETC | | |
封裝/外殼：16-SOIC（0.295"，7.50mm 寬） 功能：異步，同步 包裝：托盤 描述：IC FIFO REGISTER 4X64 3ST 16SOIC 集成電路（IC） FIFO 存儲(chǔ)器 | ETC 知名廠家 | ETC | | |
4-bit x 64-word FIFO register; 3-state | ETC 知名廠家 | ETC | | |
Dual D Flip-Flop with Set and Reset 文件：116.7 Kbytes Page：7 Pages | ONSEMI 安森美半導(dǎo)體 | | ||
Dual D-Type Flip Flop Preset and Clear 文件：234.14 Kbytes Page：9 Pages | TOSHIBA 東芝 | | ||
CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear 文件：312.68 Kbytes Page：10 Pages | TOSHIBA 東芝 | | ||
DUAL D-TYPE FLIP FLOP PRESET AND CLEAR 文件：236.41 Kbytes Page：6 Pages | TOSHIBA 東芝 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：193.4 Kbytes Page：22 Pages | Philips 飛利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飛利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：798.65 Kbytes Page：19 Pages | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | | ||
74HC CMOS logic IC series | TOSHIBA 東芝 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：193.4 Kbytes Page：22 Pages | Philips 飛利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飛利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飛利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：193.4 Kbytes Page：22 Pages | Philips 飛利浦 | |
74HC74產(chǎn)品屬性
- 類型
描述
- 型號(hào)
74HC74
- 制造商
Panasonic Industrial Company
- 功能描述
IC
| IC供應(yīng)商 | 芯片型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
恩XP |
三年內(nèi) |
SOP3.9MM |
1983 |
只做原裝正品 |
|||
恩XP |
24+ |
NA/ |
8735 |
原廠直銷,現(xiàn)貨供應(yīng),賬期支持! |
|||
ON/安森美 |
25+ |
TSSOP14 |
54648 |
百分百原裝現(xiàn)貨 實(shí)單必成 歡迎詢價(jià) |
|||
M |
24+ |
SOP14 |
20000 |
全新原廠原裝，進(jìn)口正品現(xiàn)貨，正規(guī)渠道可含稅??！ |
|||
恩XP |
24+ |
SOP14 |
7850 |
只做原裝正品現(xiàn)貨或訂貨假一賠十! |
|||
恩XP |
24+ |
SOP-14 |
90000 |
一級(jí)代理商進(jìn)口原裝現(xiàn)貨、價(jià)格合理 |
|||
恩XP |
2008+ |
TSSOP |
5000 |
一級(jí)代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
|||
NATIONAL |
24+/25+ |
2118 |
原裝正品現(xiàn)貨庫存價(jià)優(yōu) |
||||
Nexperia |
2024+ |
SOP3.9MM |
500000 |
誠信服務(wù),絕對(duì)原裝原盤 |
|||
NEXPERIA |
SOP14 |
50000 |
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74HC74數(shù)據(jù)表相關(guān)新聞
74HC74PW,118
74HC74PW,118
2023-7-1074HC7541D緩沖器和線路驅(qū)動(dòng)器原裝正品優(yōu)勢(shì)現(xiàn)貨
TTL 8 Input 8 Output Non-Inverting 緩沖器和線路驅(qū)動(dòng)器 ， 8 Input 8 Output 3.6 V 緩沖器和線路驅(qū)動(dòng)器 ， 8 Output Non-Inverting 緩沖器和線路驅(qū)動(dòng)器 ， TSSOP-20 緩沖器和線路驅(qū)動(dòng)器 ， SOT-23-6 2 Input - 40 C Non-Inverting 緩沖器和線路驅(qū)動(dòng)器 ， SO-14 緩沖器和線路驅(qū)動(dòng)器
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2020-2-1774HC595D，NXP全新19+原裝現(xiàn)貨
74HC595D，2500/盤，NXP全新19+原裝現(xiàn)貨，封裝SOP16。 深圳永貝爾科技，誠信經(jīng)營，聯(lián)系電話：0755-82566736/ QQ:3293984323，祝商祺！
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DdatasheetPDF頁碼索引
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