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CMOS Presettable Up/Down Counter

Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d

CMOS PRESETTABLE UP/DOWN COUNTER

文件：1.03602 Mbytes Page：18 Pages

CMOS 可預(yù)置加/減計數(shù)器

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

CMOS PRESETTABLE UP/DOWN COUNTER

文件：302.49 Kbytes Page：7 Pages

Presettable Binary/Decade Up/Down Counter

General Description The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte

Heyco-Flex? VI Liquid Tight Conduit Fittings

文件：156.61 Kbytes Page：1 Pages

TO-8B CASCADABLE AR4029 AMPLIFIER

文件：125.91 Kbytes Page：1 Pages