国产精品久久久久无码av色戒,大帝av在线一区二区三区,国产肥熟女视频一区二区三区,大陆少妇xxxx做受,被黑人猛躁10次高潮视频

FEATURES

· Member of the Texas Instruments Widebus?

Family

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

- 2000-V Human-Body Model (A114-A)

- 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 12-bit to 24-bit bus exchanger is designed for

1.65-V to 3.6-V VCC operation.

The SN74ALVCH16271 is intended for applications in

which two separate data paths must be multiplexed

onto, or demultiplexed from, a single data path. This

device is particularly suitable as an interface

between conventional DRAMs and high-speed

microprocessors.

A data is stored in the internal A-to-B registers on the

low-to-high transition of the clock (CLK) input,

provided that the clock-enable (CLKENA) inputs are

low. Proper control of these inputs allows two

sequential 12-bit words to be presented as a 24-bit

word on the B port.

Transparent latches in the B-to-A path allow

asynchronous operation to maximize memory access

throughput. These latches transfer data when the

latch-enable (LE) inputs are low. The select (SEL)

line selects 1B or 2B data for the A outputs. Data flow

is controlled by the active-low output enables (OEA,

OEB).

line space

To ensure the high-impedance state during power up or power down, the output enables should be tied to VCC

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the

driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.