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位置:SN74ALVCH16270DLR.B > SN74ALVCH16270DLR.B詳情

SN74ALVCH16270DLR.B中文資料

廠家型號

SN74ALVCH16270DLR.B

文件大小

275.06Kbytes

頁面數(shù)量

15

功能描述

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74ALVCH16270DLR.B數(shù)據(jù)手冊規(guī)格書PDF詳情

FEATURES

· Member of the Texas Instruments Widebus?

Family

· EPIC? (Enhanced-Performance Implanted

CMOS) Submicron Process

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

DESCRIPTION

This 12-bit to 24-bit registered bus exchanger is

designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16270 is used in applications in

which data must be transferred from a narrow

high-speed bus to a wide lower-frequency bus.

The device provides synchronous data exchange

between the two ports. Data is stored in the internal

registers on the low-to-high transition of the clock

(CLK) input when the appropriate CLKEN inputs are

low. The select (SEL) line selects 1B or 2B data for

the A outputs. For data transfer in the A-to-B

direction, a two-stage pipeline is provided in the

A-to-1B path, with a single storage register in the

A-to-2B path. Proper control of the CLKENA inputs

allows two sequential 12-bit words to be presented

synchronously as a 24-bit word on the B port. Data

flow is controlled by the active-low output enables

(OEA, OEB). The control terminals are registered to

synchronize the bus-direction changes with CLK.

To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as

possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined

by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the

outputs cannot be determined prior to the arrival of the first clock pulse.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16270 is characterized for operation from -40°C to 85°C.

更新時間:2025-9-22 15:04:00
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