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FEATURES

· Member of the Texas Instruments Widebus?

Family

· Operates From 1.65 V to 3.6 V

· Max tpd of 5 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 12-bit to 24-bit registered bus exchanger is

designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16269 is used in applications in

which two separate ports must be multiplexed onto,

or demultiplexed from, a single port. The device is

particularly suitable as an interface between

synchronous DRAMs and high-speed

microprocessors.

Data is stored in the internal B-port registers on the

low-to-high transition of the clock (CLK) input when

the appropriate clock-enable (CLKENA) inputs are

low. Proper control of these inputs allows two

sequential 12-bit words to be presented as a 24-bit

word on the B port. For data transfer in the B-to-A

direction, a single storage register is provided. The

select (SEL) line selects 1B or 2B data for the A

outputs. The register on the A output permits the

fastest possible data transfer, extending the period

during which the data is valid on the bus. The control

terminals are registered so that all transactions are

synchronous with CLK. Data flow is controlled by the

active-low output enables (OEA, OEB1, OEB2).