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位置:CLVC374AQPWRG4Q1.B > CLVC374AQPWRG4Q1.B詳情

CLVC374AQPWRG4Q1.B中文資料

廠家型號(hào)

CLVC374AQPWRG4Q1.B

文件大小

660.88Kbytes

頁(yè)面數(shù)量

16頁(yè)

功能描述

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

CLVC374AQPWRG4Q1.B數(shù)據(jù)手冊(cè)規(guī)格書(shū)PDF詳情

1FEATURES

· Qualified for Automotive Applications

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Operates From 2 V to 3.6 V

· Inputs Accept Voltages to 5.5 V

· Max tpd of 8.5 ns at 3.3 V

· Typical VOLP (Output Ground Bounce) < 0.8 V

at VCC = 3.3 V, TA = 25°C

· Typical VOHV (Output VOH Undershoot) > 2 V

at VCC = 3.3 V, TA = 25°C

· Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With 3.3-V VCC)

· Ioff Supports Partial-Power-Down Mode

Operation

DESCRIPTION/ORDERING INFORMATION

The SN74LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance

loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional

bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)

inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in

a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

更新時(shí)間:2025-9-21 15:16:00
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TI/德州儀器
25+
原廠封裝
10280
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TI/德州儀器
25+
原廠封裝
10280
TI/德州儀器
25+
原廠封裝
9999
TI/德州儀器
25+
原廠封裝
10280
TexasInstruments
18+
ICBUFF/DVRTRPLN-INVUS8
6580
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TI
16+
VSSOP
10000
原裝正品
Texas Instruments
24+
US8
65200
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TI
20+
SOP-8
3000
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TI(德州儀器)
2021+
VSSOP-8
499
TI
22+
US8
9000
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