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Medium-density performance line Arm?-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features ? Arm? 32-bit Cortex?-M3 CPU core – 72 MHz maximum frequency,? 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division ? Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM ? Clock, reset and sup

Medium-density performance line Arm?-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features ? Arm? 32-bit Cortex?-M3 CPU core – 72 MHz maximum frequency,? 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division ? Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM ? Clock, reset and sup