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SN74LS37價(jià)格
參考價(jià)格:¥2.4740
型號(hào):SN74LS373DW 品牌:Texas 備注:這里有SN74LS37多少錢,2025年最近7天走勢(shì),今日出價(jià),今日競(jìng)價(jià),SN74LS37批發(fā)/采購(gòu)報(bào)價(jià),SN74LS37行情走勢(shì)銷售排行榜,SN74LS37報(bào)價(jià)。型號(hào) | 功能描述 | 生產(chǎn)廠家&企業(yè) | LOGO | 操作 |
---|---|---|---|---|
SN74LS37 | QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS 文件:249.42 Kbytes Page:7 Pages | TI 德州儀器 | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托羅拉 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托羅拉 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托羅拉 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托羅拉 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州儀器 | |||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI2 德州儀器 | |||
4-BIT D LATCH The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo | Motorola 摩托羅拉 | |||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI2 德州儀器 | |||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI2 德州儀器 | |||
4-BIT D LATCH The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo | Motorola 摩托羅拉 | |||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI2 德州儀器 | |||
LOW POWER SCHOTTKY The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. ? 8-Bit High Speed Parallel Registers ? Positive Edge-Triggered D-Type Flip Flops ? F | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
LOW POWER SCHOTTKY The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. ? 8-Bit High Speed Parallel Registers ? Positive Edge-Triggered D-Type Flip Flops ? F | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
LOW POWER SCHOTTKY The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. ? 8-Bit High Speed Parallel Registers ? Positive Edge-Triggered D-Type Flip Flops ? F | ONSEMI 安森美半導(dǎo)體 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托羅拉 | |||
QUAD 2-INPUT NAND BUFFER
| Motorola 摩托羅拉 | |||
QUAD 2-INPUT NAND BUFFER
| Motorola 摩托羅拉 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:331.48 Kbytes Page:24 Pages | TI 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:242.39 Kbytes Page:10 Pages | TI 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:694.69 Kbytes Page:28 Pages | TI 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:1.43118 Mbytes Page:30 Pages | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:694.69 Kbytes Page:28 Pages | TI 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:242.39 Kbytes Page:10 Pages | TI 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:331.48 Kbytes Page:24 Pages | TI 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:1.43118 Mbytes Page:30 Pages | TI1 德州儀器 | |||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件:694.69 Kbytes Page:28 Pages | TI 德州儀器 |
替換型號(hào) | 功能描述 | 生產(chǎn)廠家&企業(yè) | LOGO | 操作 |
---|---|---|---|---|
TRI-STATEE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops | NSCNational Semiconductor (TI) 美國(guó)國(guó)家半導(dǎo)體美國(guó)國(guó)家半導(dǎo)體公司 | NSC | ||
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS | TI 德州儀器 | TI | ||
Quadruple 2-input Positive NAND Buffers | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | ||
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops | FairchildFairchild Semiconductor 仙童半導(dǎo)體飛兆/仙童半導(dǎo)體公司 | Fairchild | ||
Quadruple 2-input Positive NAND Buffers | RENESAS 瑞薩 | RENESAS | ||
Ouadruple 2-input Positive NAND Gates | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | ||
Quadruple 2-input Positive NAND Buffers | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | ||
Quadruple 2-input Positive NAND Buffers | RENESAS 瑞薩 | RENESAS |
SN74LS37產(chǎn)品屬性
- 類型
描述
- 型號(hào)
SN74LS37
- 功能描述
閉鎖 Octal D-Type
- RoHS
否
- 制造商
Micrel
- 電路數(shù)量
1
- 邏輯類型
CMOS
- 邏輯系列
TTL
- 極性
Non-Inverting
- 輸出線路數(shù)量
9
- 電源電壓-最大
12 V
- 電源電壓-最小
5 V
- 最大工作溫度
+ 85 C
- 最小工作溫度
- 40 C
- 封裝/箱體
SOIC-16
- 封裝
Reel
IC供應(yīng)商 | 芯片型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
TI |
23+ |
SO-20 |
7000 |
絕對(duì)全新原裝!100%保質(zhì)量特價(jià)!請(qǐng)放心訂購(gòu)! |
|||
MMI |
24+ |
CDIP20 |
23000 |
只做正品原裝現(xiàn)貨 |
|||
2023+ |
7.2mm |
3000 |
進(jìn)口原裝現(xiàn)貨 |
||||
24+ |
SON-6 |
6000 |
美國(guó)德州儀器TEXASINSTRUMENTS原廠代理輝華拓展內(nèi)地現(xiàn) |
||||
TI/德州儀器 |
24+ |
SOP |
3580 |
原裝現(xiàn)貨/15年行業(yè)經(jīng)驗(yàn)歡迎詢價(jià) |
|||
TI/德州儀器 |
20+ |
SOIC-20_300mil |
6000 |
全新原裝 |
|||
ADI |
23+ |
SOP-5.2 |
7000 |
||||
TI(德州儀器) |
2021+ |
SOIC-20 |
499 |
||||
TI |
23+ |
SOP-20 |
16800 |
一級(jí)分銷商 |
|||
TI |
24+ |
DIP-20 |
65200 |
原裝現(xiàn)貨/放心購(gòu)買 |
SN74LS37芯片相關(guān)品牌
SN74LS37規(guī)格書下載地址
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- SN74LS374NS
- SN74LS374NDS
- SN74LS374ND
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- SN74LS374JS
- SN74LS374JDS
- SN74LS374JD
- SN74LS374J
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- SN74LS373NS
- SN74LS373NDS
- SN74LS373ND
- SN74LS373N
- SN74LS373JS
- SN74LS373JDS
- SN74LS373JD
- SN74LS373J
- SN74LS373
- SN74LS368N
- SN74LS368J
- SN74LS368ANS
- SN74LS368ANDS
- SN74LS368AND
- SN74LS368AN
- SN74LS368AJS
- SN74LS368AJDS
- SN74LS368AJD
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