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SN74LS112AN價格
參考價格:¥1.7827
型號:SN74LS112AN 品牌:TI 備注:這里有SN74LS112AN多少錢,2025年最近7天走勢,今日出價,今日競價,SN74LS112AN批發(fā)/采購報價,SN74LS112AN行情走勢銷售排行榜,SN74LS112AN報價。型號 | 功能描述 | 生產(chǎn)廠家&企業(yè) | LOGO | 操作 |
---|---|---|---|---|
SN74LS112AN | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件:300.4 Kbytes Page:9 Pages | TI 德州儀器 | ||
SN74LS112AN | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州儀器 | ||
SN74LS112AN | DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI1 德州儀器 | ||
SN74LS112AN | 封裝/外殼:16-DIP(0.300",7.62mm) 功能:設置(預設)和復位 包裝:卷帶(TR)剪切帶(CT)Digi-Reel? 得捷定制卷帶 描述:IC FF JK TYPE DUAL 1BIT 16DIP 集成電路(IC) 觸發(fā)器 | TI2 德州儀器 | ||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI1 德州儀器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州儀器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州儀器 | |||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI1 德州儀器 | |||
封裝/外殼:16-SOIC(0.209",5.30mm 寬) 功能:設置(預設)和復位 包裝:卷帶(TR)剪切帶(CT)Digi-Reel? 得捷定制卷帶 描述:IC FF JK TYPE DUAL 1BIT 16SO 集成電路(IC) 觸發(fā)器 | TI2 德州儀器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州儀器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州儀器 | |||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FairchildFairchild Semiconductor 仙童半導體飛兆/仙童半導體公司 | |||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) ● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....) | HitachiHitachi Semiconductor 日立日立公司 | |||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | Motorola 摩托羅拉 | |||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FairchildFairchild Semiconductor 仙童半導體飛兆/仙童半導體公司 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件:300.4 Kbytes Page:9 Pages | TI 德州儀器 |
替換型號 | 功能描述 | 生產(chǎn)廠家&企業(yè) | LOGO | 操作 |
---|---|---|---|---|
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola 摩托羅拉 | Motorola | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州儀器 | TI | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FairchildFairchild Semiconductor 仙童半導體飛兆/仙童半導體公司 | Fairchild | ||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | ||
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS | NSCNational Semiconductor (TI) 美國國家半導體美國國家半導體公司 | NSC | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FairchildFairchild Semiconductor 仙童半導體飛兆/仙童半導體公司 | Fairchild | ||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | ||
Ouadruple 2-input Positive NAND Gates | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州儀器 | TI | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州儀器 | TI |
SN74LS112AN產(chǎn)品屬性
- 類型
描述
- 型號
SN74LS112AN
- 功能描述
觸發(fā)器 Dual Neg-Edge-Trig J-K Flip-Flop
- RoHS
否
- 制造商
Texas Instruments
- 電路數(shù)量
2
- 邏輯系列
SN74
- 邏輯類型
D-Type Flip-Flop
- 極性
Inverting, Non-Inverting
- 輸入類型
CMOS
- 傳播延遲時間
4.4 ns
- 高電平輸出電流
- 16 mA
- 低電平輸出電流
16 mA
- 電源電壓-最大
5.5 V
- 最大工作溫度
+ 85 C
- 安裝風格
SMD/SMT
- 封裝/箱體
X2SON-8
- 封裝
Reel
IC供應商 | 芯片型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
TI/德州儀器 |
1948+ |
DIP16 |
6852 |
只做原裝正品現(xiàn)貨!或訂貨假一賠十! |
|||
TI/德州儀器 |
23+ |
DIP16 |
30000 |
原裝現(xiàn)貨,假一賠十. |
|||
Texas Instruments |
25+ |
16-PDIP |
9350 |
獨立分銷商 公司只做原裝 誠心經(jīng)營 免費試樣正品保證 |
|||
TI/德州儀器 |
22+ |
DIP-16 |
500000 |
原裝現(xiàn)貨支持實單價優(yōu)/含稅 |
|||
TI |
25+ |
高頻管 |
18000 |
原廠直接發(fā)貨進口原裝 |
|||
TI |
92+ |
DIP-16 |
18 |
原裝現(xiàn)貨海量庫存歡迎咨詢 |
|||
TI/德州儀器 |
20+ |
DIP-16 |
6000 |
全新原裝 |
|||
TI/德州儀器 |
23+ |
DIP-16 |
12700 |
買原裝認準中賽美 |
|||
TI/德州儀器 |
25+ |
DIP-16 |
4987 |
強勢庫存!絕對原裝公司現(xiàn)貨! |
|||
TI |
96 |
80 |
公司優(yōu)勢庫存 熱賣中!! |
SN74LS112AN芯片相關品牌
SN74LS112AN規(guī)格書下載地址
SN74LS112AN參數(shù)引腳圖相關
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SN74LS112AN數(shù)據(jù)表相關新聞
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2019-6-24
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