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4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes Page：19 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes Page：19 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：497.3 Kbytes Page：20 Pages

4-bit D-type Register (with 3-state Outputs)

Description The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The input disable allows the

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

TTL HD74/HD74S Series

TRI-STATE Quad Registers

文件：131.38 Kbytes Page：6 Pages

TRI-STATE Quad Registers