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Presettable synchronous 4-bit binary counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Synchronous counting and loading ? Two count enable inputs for n-bit cascading ? Positive

Philips

飛利浦

Presettable synchronous 4-bit binary counter; asynchronous reset

1. General description The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HI

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

Presettable synchronous 4-bit binary counter; asynchronous reset

1. General description The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HI

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

Presettable synchronous 4-bit binary counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Synchronous counting and loading ? Two count enable inputs for n-bit cascading ? Positive

Philips

飛利浦

Presettable synchronous 4-bit binary counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Synchronous counting and loading ? Two count enable inputs for n-bit cascading ? Positive

Philips

飛利浦

更新時(shí)間:2025-8-20 11:00:01
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