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3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20 pin SOIC ? Pb (lead) free package ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock or

封裝/外殼：20-SOIC（0.295"，7.50mm 寬） 包裝：卷帶（TR） 描述：IC VCXO PLL CLK SYNTH 20-SOIC 集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器

3.3 V Communications Clock PLL

Description The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20 pin SOIC ? Pb (lead) free package ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock or

3.3 V Communications Clock PLL

Description The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20 pin SOIC ? Pb (lead) free package ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock or