国产精品久久久久无码av色戒,大帝av在线一区二区三区,国产肥熟女视频一区二区三区,大陆少妇xxxx做受,被黑人猛躁10次高潮视频

3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH 5 VOLT TOLERANT I/O

文件：87.91 Kbytes Page：6 Pages

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES ? Wide supply voltage range of 1.2 to 3.6 V ? In accordance with JEDEC standard no. 8-1A ? Inputs accept voltages up to 5.5 V ? CMOS l

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES ? Wide supply voltage range of 1.2 to 3.6 V ? In accordance with JEDEC standard no. 8-1A ? Inputs accept voltages up to 5.5 V ? CMOS l

3-to-8 line decoder/demultiplexer; inverting

文件：184.85 Kbytes Page：16 Pages