位置:首頁 > IC中文資料第1076頁 > IDT2309-1H
型號 | 功能描述 | 生產(chǎn)廠家&企業(yè) | LOGO | 操作 |
---|---|---|---|---|
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
封裝/外殼:16-SOIC(0.154",3.90mm 寬) 包裝:管件 描述:IC CLK BUFFER ZD HI DRV 16-SOIC 集成電路(IC) 時鐘發(fā)生器,PLL,頻率合成器 | ETC 知名廠家 | ETC | ||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件:125.72 Kbytes Page:10 Pages | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件:125.72 Kbytes Page:10 Pages | IDT | |||
封裝/外殼:16-SOIC(0.154",3.90mm 寬) 包裝:管件 描述:IC CLK BUFFER ZD HI DRV 16-SOIC 集成電路(IC) 時鐘發(fā)生器,PLL,頻率合成器 | ETC 知名廠家 | ETC | ||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件:125.72 Kbytes Page:10 Pages | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件:125.72 Kbytes Page:10 Pages | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件:125.72 Kbytes Page:10 Pages | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件:125.72 Kbytes Page:10 Pages | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件:125.72 Kbytes Page:10 Pages | IDT | |||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件:125.72 Kbytes Page:10 Pages | IDT |
IDT2309-1H產(chǎn)品屬性
- 類型
描述
- 型號
IDT2309-1H
- 功能描述
IC CLK BUFFER ZD HI DRV 16-SOIC
- RoHS
否
- 類別
集成電路(IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器
- 系列
-
- 產(chǎn)品變化通告
Product Discontinuation 04/May/2011
- 標準包裝
96
- 系列
-
- 類型
時鐘倍頻器,零延遲緩沖器
- PLL
帶旁路
- 輸入
LVTTL
- 輸出
LVTTL
- 電路數(shù)
1 比率 -
- 1
8 差分 -
- 輸出
無/無 頻率 -
- 最大
133.3MHz
- 除法器/乘法器
是/無
- 電源電壓
3 V ~ 3.6 V
- 工作溫度
0°C ~ 70°C
- 安裝類型
表面貼裝
- 封裝/外殼
16-TSSOP(0.173,4.40mm 寬)
- 供應(yīng)商設(shè)備封裝
16-TSSOP
- 包裝
管件
- 其它名稱
23S08-5HPGG
IC供應(yīng)商 | 芯片型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
IDT |
24+ |
SSOP |
9600 |
原裝現(xiàn)貨,優(yōu)勢供應(yīng),支持實單! |
|||
IDT |
2016+ |
TSSOP-1 |
6528 |
只做進口原裝現(xiàn)貨!假一賠十! |
|||
IDT |
22+ |
SOP |
5000 |
全新原裝現(xiàn)貨!自家?guī)齑? |
|||
IDT, Integrated Device Technol |
24+ |
16-SOIC |
56200 |
一級代理/放心采購 |
|||
IDT |
24+ |
SSOP |
2987 |
絕對全新原裝現(xiàn)貨供應(yīng)! |
|||
IDT |
2447 |
SSOP |
100500 |
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨 |
|||
23+ |
原廠封裝 |
9888 |
專做原裝正品,假一罰百! |
||||
IDT |
05+ |
原廠原裝 |
7217 |
只做全新原裝真實現(xiàn)貨供應(yīng) |
|||
IDT |
24+ |
TSSOP |
101 |
||||
INTEGRATEDDEVICETECHNOLO |
1922+ |
OEM封裝 |
5689 |
原裝進口現(xiàn)貨庫存專業(yè)工廠研究所配單供貨 |
IDT2309-1H芯片相關(guān)品牌
IDT2309-1H規(guī)格書下載地址
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