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Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

Quad D latch

The BU4042B is a four-circuit D latch with a common clock line and separate data input terminals. When the polarity input is set to “H”, input (D) is presented to output (Q) as is, as long as the clock input is rising, and when the clock input falls, output (Q) holds input (D) at that point. Whil

RF Filter

文件：198.71 Kbytes Page：3 Pages

Wide Selection of Panel Seal Boots

文件：84.84 Kbytes Page：1 Pages

CMOS Quad Clocked D Latch

文件：197.52 Kbytes Page：3 Pages