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All Devices Discontinued

Features ?HIGH PERFORMANCE E2CMOS?TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS? Advanced CMOS Technology ?50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

High Performance E2CMOS PLD Generic Array Logic?

文件：654.14 Kbytes Page：24 Pages

High Performance E2CMOS PLD

文件：340.72 Kbytes Page：23 Pages

封裝/外殼：20-DIP（0.300"，7.62mm） 包裝：管件 描述：IC CPLD 8MC 7.5NS 20DIP 集成電路（IC） CPLD（復(fù)雜可編程邏輯器件）

All Devices Discontinued

Features ?HIGH PERFORMANCE E2CMOS?TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS? Advanced CMOS Technology ?50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

High Performance E2CMOS PLD Generic Array Logic?

文件：654.14 Kbytes Page：24 Pages

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features ?HIGH PERFORMANCE

High Performance E2CMOS PLD Generic Array Logic?

文件：293.59 Kbytes Page：8 Pages

High Performance E2CMOS PLD Generic Array Logic?

文件：395.51 Kbytes Page：22 Pages

High Performance E2CMOS PLD Generic Array Logic?

文件：654.14 Kbytes Page：24 Pages

High Performance E2CMOS PLD Generic Array Logic?

文件：339.82 Kbytes Page：23 Pages