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CY7C144價(jià)格

參考價(jià)格：￥547.2085

型號(hào)：CY7C1440AV25-167BZXC 品牌：Cynergy 3 備注：這里有CY7C144多少錢，2025年最近7天走勢(shì)，今日出價(jià)，今日競(jìng)價(jià)，CY7C144批發(fā)/采購(gòu)報(bào)價(jià)，CY7C144行情走勢(shì)銷售排行榜，CY7C144報(bào)價(jià)。

型號(hào)	功能描述	生產(chǎn)廠家企業(yè)	LOGO
CY7C144	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy 文件：391.37 Kbytes Page：19 Pages	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C144	8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY 文件：607.9 Kbytes Page：20 Pages	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C144	8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY	Infineon 英飛凌	Infineon
CY7C1440AV33	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-167AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-167BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-167BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-200AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-200BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-200BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-250AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-250BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1440AV33-250BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-100AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-100AXI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-100BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-100BZI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-100BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-100BZXI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-133AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-133AXI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-133BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-133BZI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-133BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV25-133BZXI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1441AV33	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-167AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-167BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-167BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-200AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-200BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-200BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-250AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-250BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1442AV33-250BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-100AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-100AXI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-100BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-100BZI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-100BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-100BZXI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-133AXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-133AXI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-133BZC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-133BZI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-133BZXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1443AV33-133BZXI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1446AV33	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1446AV33-167BGC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1446AV33-167BGXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1446AV33-200BGC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1446AV33-200BGXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1446AV33-250BGC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1446AV33-250BGXC	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1447AV33	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1447AV33-100BGC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1447AV33-100BGI	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress
CY7C1447AV33-100BGXC	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)	CypressCypress Semiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司	Cypress

CY7C144產(chǎn)品屬性

類型
描述
型號(hào)
CY7C144
功能描述
靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB(1Mx36) 2.5v 167MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器
RoHS
否
制造商
Cypress Semiconductor
存儲(chǔ)容量
16 Mbit
組織
1 M x 16
訪問時(shí)間
55 ns
電源電壓-最大
3.6 V
電源電壓-最小
2.2 V
最大工作電流
22 uA
最大工作溫度
+ 85 C
最小工作溫度
- 40 C
安裝風(fēng)格
SMD/SMT
封裝/箱體
TSOP-48
封裝
Tray

CY7C144供應(yīng)商更多...

更新時(shí)間：2025-9-20 14:33:00

IC供應(yīng)商	芯片型號(hào)	品牌	批號(hào)	封裝	庫(kù)存	備注	價(jià)格
深圳市河鋒鑫科技有限公司	CY7C1440AV25167BZXC	Cypress	22+	165FBGA (15x17)	9000	原廠渠道,現(xiàn)貨配單	詢價(jià)
深圳市科芯源微電子有限公司	CY7C1440AV25-167BZC	CYPRESS/賽普拉斯	25+	BGA	102	原裝正品,假一罰十!	詢價(jià)
深圳市中遠(yuǎn)芯科技有限公司	CY7C144-55JXCT	CYPRESS/賽普拉斯	07+	PLCC	2950	原裝現(xiàn)貨價(jià)格優(yōu)勢(shì)	詢價(jià)
深圳市冠億通科技有限公司	CY7C1441KV33-133AXI	Cypress(賽普拉斯)	25+		5000	只做原裝假一罰百可開票可售樣	詢價(jià)
深圳市凌旭科技有限公司	CY7C144-55JXC	CY	21+	PLCC	1576	十年信譽(yù),只做原裝,有掛就有現(xiàn)貨!	詢價(jià)
深圳市得捷芯城科技有限公司	CY7C1441KV33-133AXIT	CYPRESS(賽普拉斯)	24+	LQFP-100	5591	百分百原裝正品,可原型號(hào)開票	詢價(jià)
深圳市達(dá)恩科技有限公司	CY7C144-55JXCT	CYPRESS/賽普拉斯	24+	PLCC	2950	全部原裝現(xiàn)貨優(yōu)勢(shì)產(chǎn)品	詢價(jià)
深圳市納艾斯科技有限公司	CY7C144AV-25AIT	CYPRESS	24+	TQFP	8000	只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開13%增	詢價(jià)
中天科工半導(dǎo)體（深圳）有限公司	CY7C1440AV33-167AXC	CYPRESS/賽普拉斯	25+	QFP100	12496	CYPRESS/賽普拉斯原裝正品CY7C1440AV33-167AXC即刻詢購(gòu)立享優(yōu)惠#長(zhǎng)期有貨	詢價(jià)
富凱科技(深圳）有限公司	CY7C144-55JXCT	CYPRESS10	25+	PLCC	20000	北京	詢價(jià)

CY7C144芯片相關(guān)品牌

CY7C144規(guī)格書下載地址

CY7C144參數(shù)引腳圖相關(guān)

DC-AC
d880
d870
d828
d7805
d7804
d641
d609
d415
d408
d403
d402
d325
d2007
d2004
d2002
d126
d1004
d1002
c波段
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CY7C196
CY7C195
CY7C194
CY7C192
CY7C188
CY7C187
CY7C186
CY7C185
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CY7C179
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CY7C164
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CY7C148
CY7C147
CY7C1460AV25-200BZI
CY7C1460AV25-167BZXI
CY7C1460AV25-167BZC
CY7C1460AV25-167AXC
CY7C146
CY7C145
CY7C144V9
CY7C144E-55JXC
CY7C144E-55AXC
CY7C144AV-25AXC
CY7C1444AV33-250AXI
CY7C1444AV33-167AXC
CY7C1441AV33-133BZXI
CY7C1441AV33-133BZI
CY7C1441AV33-133AXI
CY7C1441AV33-133AXC
CY7C1441AV25-133BZXI
CY7C1440AV33-250BZXI
CY7C1440AV33-250AXC
CY7C1440AV33-167AXC
CY7C1440AV25-250BZXI
CY7C1440AV25-167BZXC
CY7C143
CY7C1426KV18-300BZXC
CY7C1426KV18-300BZC
CY7C1426KV18-250BZXC
CY7C1426KV18-250BZC
CY7C1425KV18-250BZXI
CY7C1425KV18-250BZXC
CY7C1425KV18-250BZC
CY7C1423KV18-300BZXC
CY7C1423KV18-300BZC
CY7C1423KV18-250BZXC
CY7C1423KV18-250BZC
CY7C1420KV18-300BZXC
CY7C1420KV18-250BZXI
CY7C1420KV18-250BZXC
CY7C1420KV18-250BZC
CY7C142
CY7C1418KV18-300BZXC
CY7C1418KV18-300BZC
CY7C1418KV18-250BZXC
CY7C1418KV18-250BZI
CY7C1418KV18-250BZC
CY7C141
CY7C140
CY7C139
CY7C138
CY7C136
CY7C135
CY7C133
CY7C132
CY7C131
CY7C130
CY7C129
CY7C109
CY7C107
CY7C057
CY7C038
CY7C037
CY7C028
CY7C027

CY7C144數(shù)據(jù)表相關(guān)新聞

CY7C15632KV18-500BZXI
進(jìn)口代理
2024-11-25
CY7C1565KV18-500BZXI
進(jìn)口代理
2023-10-24
CY7C1462AV33-167AXC 原裝現(xiàn)貨
CY7C1462AV33-167AXC 可做含稅，支持實(shí)單
2021-9-18
CY7C1399B-12ZC 十年IC，一家專業(yè)軍工級(jí)IC供貨商
CY7C1399B-12ZC CY7C1399B-12ZC，ALTERA（阿爾特拉），軍工級(jí)IC專業(yè)優(yōu)勢(shì)渠道
2020-7-16
CY7C1399B-12ZC十年IC，一家專業(yè)軍工級(jí)IC供貨商
CY7C1399B-12ZC十年IC，一家專業(yè)軍工級(jí)IC供貨商
2020-7-15
CY7C1370D-167AXI產(chǎn)品資料 CYPRESS/賽普拉斯
CY7C1370D-167AXI產(chǎn)品資料
2020-6-28

DdatasheetPDF頁(yè)碼索引

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