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CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ? Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

CMOS Dual 4-Stage Static Shift Register

Features: ? Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ? Fully static operation ? 8 master-slave flip-flops plus input and output buffering ? 100% tested for quiescent current at 20 V ?5.V, 10-V, and 15-V parametric ratings ? Standardized, symmetr

封裝/外殼：16-TSSOP（0.173"，4.40mm 寬） 功能：串行至并行 包裝：管件 描述：IC DUAL STATIC SHFT REG 16-TSSOP 集成電路（IC） 移位寄存器

CMOS Dual 4-Stage Static Shift Register

文件：521.58 Kbytes Page：11 Pages

CMOS Dual 4-stage Static Shift Register

文件：884.25 Kbytes Page：15 Pages

CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ? Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

CMOS Dual 4-Stage Static Shift Register

Features: ? Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ? Fully static operation ? 8 master-slave flip-flops plus input and output buffering ? 100% tested for quiescent current at 20 V ?5.V, 10-V, and 15-V parametric ratings ? Standardized, symmetr

CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ? Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

CMOS Dual 4-Stage Static Shift Register

Features: ? Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ? Fully static operation ? 8 master-slave flip-flops plus input and output buffering ? 100% tested for quiescent current at 20 V ?5.V, 10-V, and 15-V parametric ratings ? Standardized, symmetr

封裝/外殼：16-TSSOP（0.173"，4.40mm 寬） 功能：串行至并行 包裝：卷帶（TR） 描述：IC DUAL STATIC SHFT REG 16-TSSOP 集成電路（IC） 移位寄存器

CMOS Dual 4-stage Static Shift Register

文件：884.25 Kbytes Page：15 Pages

CMOS Dual 4-Stage Static Shift Register

文件：521.58 Kbytes Page：11 Pages

CMOS Dual 4-stage Static Shift Register

文件：884.25 Kbytes Page：15 Pages

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Description CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages

EPDM Snap-In Liquid Tight Bushings

文件：95.85 Kbytes Page：1 Pages

EPDM Snap-In Liquid Tight Bushings

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EC Directives Models)

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compact and economical surface-acoustic wave ( SAW ) filter

文件：85.35 Kbytes Page：3 Pages