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封裝/外殼：28-SSOP（0.209"，5.30mm 寬） 包裝：卷帶（TR） 描述：IC CLK BUF DDR 600MHZ 1CIRC 集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí)

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

文件：197.4 Kbytes Page：13 Pages

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Description Output Features DDR I/DDR II Zero Delay Clock Buffer ? Low skew, low jitter PLL clock driver ? Max frequency supported = 400MHz (DDRII 800) ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? Programmab

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Description Output Features DDR I/DDR II Zero Delay Clock Buffer ? Low skew, low jitter PLL clock driver ? Max frequency supported = 400MHz (DDRII 800) ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? Programmab

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

文件：197.41 Kbytes Page：13 Pages

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

文件：197.41 Kbytes Page：13 Pages