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Programmable Dual-Range DC Power Supplies

文件：2.51141 Mbytes Page：6 Pages

包裝：盒 描述：DC PWR SUPPLY 0-10V 10A/0-20V 5A 測試與計(jì)量 設(shè)備 - 電源（測試，工作臺(tái)）

包裝：盒 描述：DC PWR SUPPLY 0-10V 10A/0-20V 5A 測試與計(jì)量 設(shè)備 - 電源（測試，工作臺(tái)）

Video Genlock PLL

Single and dual output models with up to 210W output power

文件：2.52949 Mbytes Page：6 Pages

Countersunk Type H Rivets

文件：105.68 Kbytes Page：1 Pages

Programmable Dual-Range DC Power Supplies

文件：2.57998 Mbytes Page：6 Pages

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Features ? Phase-detector/VCO circuit block ? Ideal for genlock system ? Reference clock range 12 kHz to 1 MHz for full output clock range ? Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions ? O

VIDEO GENLOCK PLL

Features ? Phase-detector/VCO circuit block ? Ideal for genlock system ? Reference clock range 12 kHz to 1 MHz for full output clock range ? Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions ? O

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Features ? Phase-detector/VCO circuit block ? Ideal for genlock system ? Reference clock range 12 kHz to 1 MHz for full output clock range ? Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions ? O

VIDEO GENLOCK PLL

Features ? Phase-detector/VCO circuit block ? Ideal for genlock system ? Reference clock range 12 kHz to 1 MHz for full output clock range ? Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions ? O

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

時(shí)鐘發(fā)生器及支持產(chǎn)品 VIDEO GENERATOR CLK

時(shí)鐘發(fā)生器及支持產(chǎn)品 VIDEO GENERATOR CLK

Piezoelectric load cells SlimLine Piezoelectric force transducers for tensile and compression forces of up to –20 ... 75 kN