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FemtoClock? Zero Delay Buffer/ Clock Generator for PCI Express? and Ethernet

Features ? Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications ? One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL ? One M-LVDS I/O pair (ML

封裝/外殼：56-VFQFN 裸露焊盤 包裝：托盤 描述：IC FEMTOCLOCK HCSL/MLVDS 56VFQFN 集成電路（IC） 應(yīng)用特定時鐘/定時

FemtoClock? Zero Delay Buffer/ Clock Generator for PCI Express? and Ethernet

Features ? Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications ? One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL ? One M-LVDS I/O pair (ML

FemtoClock? Zero Delay Buffer/ Clock Generator for PCI Express? and Ethernet

Features ? Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications ? One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL ? One M-LVDS I/O pair (ML

Output frequency range

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