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3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Demultiplexing capability ? Multiple input enable for easy expansion ? Ideal for memory

CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? 3-to-8 Line Decoder General The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled,

3-to-8 line decoder/demultiplexer; inverting

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple ena

3-to-8 line decoder/demultiplexer; inverting

封裝/外殼：16-SOIC（0.154"，3.90mm 寬） 包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 描述：IC DECODER 1 X 3:8 16SOIC 集成電路（IC） 信號(hào)開關(guān)，多路復(fù)用器，解碼器

74HC CMOS logic IC series

3-to-8 line decoder/demultiplexer; inverting

3 TO 8 LINE DECODER DEMULTIPLEXER

Description The 74HC138 is a high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH en

3-to-8 line decoder/demultiplexer inverting

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Demultiplexing capability ? Multiple input enable for easy expansion ? Ideal for memory

1??f?? Decoder/ Demultiplexer High??erformance Silicon??ate CMOS

文件：140.61 Kbytes Page：9 Pages

3-to-8 Line Decoder/Demultiplexer; Inverting

文件：229.08 Kbytes Page：5 Pages

3-to-8 line decoder/demultiplexer; inverting

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Demultiplexing capability ? Multiple input enable for easy expansion ? Ideal for memory

3-to-8 line decoder/demultiplexer; inverting

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This m

封裝/外殼：16-SOIC（0.154"，3.90mm 寬） 包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 描述：IC DECODER/DEMUX 1 X 3:8 16SO 集成電路（IC） 信號(hào)開關(guān)，多路復(fù)用器，解碼器

3-to-8 line decoder/demultiplexer; inverting

3-to-8 line decoder/demultiplexer; inverting

1??f?? Decoder/ Demultiplexer High??erformance Silicon??ate CMOS

文件：140.61 Kbytes Page：9 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/Demultiplexer Inverting and Noninverting

文件：765.4 Kbytes Page：19 Pages

1??f?? Decoder/ Demultiplexer High??erformance Silicon??ate CMOS

文件：140.61 Kbytes Page：9 Pages