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型號 功能描述 生產(chǎn)廠家 企業(yè) LOGO 操作
74F112

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

74F112

Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

Philips

飛利浦

74F112

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes Page：7 Pages

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

74F112

Dual JK Negative Edge-Triggered Flip-Flop

ONSEMI

安森美半導體

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes Page：7 Pages

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes Page：7 Pages

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes Page：7 Pages

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

封裝/外殼：16-SOIC（0.154"，3.90mm 寬） 功能：設置（預設）和復位 包裝：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成電路（IC） 觸發(fā)器

ONSEMI

安森美半導體

封裝/外殼：16-SOIC（0.154"，3.90mm 寬） 功能：設置（預設）和復位 包裝：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成電路（IC） 觸發(fā)器

ONSEMI

安森美半導體

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes Page：7 Pages

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

74F112產(chǎn)品屬性

  • 類型

    描述

  • 型號

    74F112

  • 制造商

    FAIRCHILD

  • 制造商全稱

    Fairchild Semiconductor

  • 功能描述

    Dual JK Negative Edge-Triggered Flip-Flop

更新時間：2025-9-18 16:43:00
IC供應商 芯片型號 品牌 批號 封裝 庫存 備注 價格
onsemi(安森美)
24+
SOP16
1583
只做原裝,提供一站式配單服務,代工代料。BOM配單
FUJITSU/富士通
24+
NA/
506
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票
FAI
24+
SOP3.9
20000
一級代理原裝現(xiàn)貨假一罰十
NS
2024
SOP
13500
16余年資質(zhì) 絕對原盒原盤代理渠道 更多數(shù)量
PHI
25+
SOP
3200
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售
NS
96
SOP-14
12
原裝現(xiàn)貨海量庫存歡迎咨詢
NS
QQ咨詢
CDIP
828
全新原裝 研究所指定供貨商
TI/德州儀器
23+
SO3.9
6105
原廠授權(quán)代理,海外優(yōu)勢訂貨渠道?？商峁┐罅繋齑?詳
FAIRCHILD
23+
SMD-SO16
9856
原裝正品,假一罰百!
PHI
24+
SOP3.9
6980
原裝現(xiàn)貨,可開13%稅票

74F112芯片相關品牌

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