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CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features ? Packaged as 28-pin SSOP, Pb-free (150 mil body) ? Synchronizes fractional clocks rising edges ? PECL IN to CMOS OUT ? Pin selectable dividers ? Zero input to output skew ? User determines the output frequency—no software needed ? Slices frequency or period ? Input clock frequen

封裝/外殼：28-SSOP（0.154"，3.90mm 寬） 包裝：卷帶（TR） 描述：IC CLK SLICER ZDB CONFIG 28-SSOP 集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features ? Packaged as 28-pin SSOP, Pb-free (150 mil body) ? Synchronizes fractional clocks rising edges ? PECL IN to CMOS OUT ? Pin selectable dividers ? Zero input to output skew ? User determines the output frequency—no software needed ? Slices frequency or period ? Input clock frequen

封裝/外殼：28-SSOP（0.154"，3.90mm 寬） 包裝：管件 描述：IC CLOCK SLICER ZD BUFFER 28SSOP 集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features ? Packaged as 28-pin SSOP, Pb-free (150 mil body) ? Synchronizes fractional clocks rising edges ? PECL IN to CMOS OUT ? Pin selectable dividers ? Zero input to output skew ? User determines the output frequency—no software needed ? Slices frequency or period ? Input clock frequen

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features ? Packaged as 28-pin SSOP, Pb-free (150 mil body) ? Synchronizes fractional clocks rising edges ? PECL IN to CMOS OUT ? Pin selectable dividers ? Zero input to output skew ? User determines the output frequency—no software needed ? Slices frequency or period ? Input clock frequen

Clock Slicer User Configurable PECL Input Zero Delay Buffer

Description The ICS527-02 Clock Slicer is the most flexible way to generate a CMOS output clock from a PECL input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer mul