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1 Features

1? Differential Analog Inputs

? Total Output Power at 10%THD+N

– 175-W Stereo into 4 Ω in BTL Configuration

– 220-W Stereo into 3 Ω in BTL Configuration

– 350-W Mono into 2 Ω in PBTL Configuration

? Total Output Power at 1%THD+N

– 140-W Stereo into 4 Ω in BTL Configuration

– 175-W Stereo into 3 Ω in BTL Configuration

– 285-W Mono into 2 Ω in PBTL Configuration

? Advanced Integrated Feedback Design with Highspeed

Gate Driver Error Correction

(PurePath? Ultra-HD)

– Signal Bandwidth up to 100 kHz for High

Frequency Content From HD Sources

– Ultra Low 0.005% THD+N at 1 W into 4 Ω and

<0.01% THD+N to Clipping

– 60 dB PSRR (BTL, No Input Signal)

– <60 μV (A-Weighted) Output Noise

– >111 dB (A Weighted) SNR

? Multiple Configurations Possible:

– Stereo, Mono, 2.1 and 4xSE

? Click and Pop Free Startup and Stop

? 90% Efficient Class-D Operation (4 Ω)

? Wide 12-V to 36-V Supply Voltage Operation

? Self-Protection Design (Including Undervoltage,

Overtemperature, Clipping, and Short Circuit

Protection) With Error Reporting

? EMI Compliant When Used With Recommended

System Design

2 Applications

? Blu-ray Disk? / DVD Receivers

? High End HTiB Systems

? AV Receivers

? High End Soundbar

? Mini Combo Systems

? Active Speakers and Subwoofers

3 Description

TPA3251 is a high performance class-D power

amplifier that enables true premium sound quality

with class-D efficiency. It features an advanced

integrated feedback design and proprietary highspeed

gate driver error correction (PurePath? Ultra-

HD). This technology allows ultra low distortion

across the audio band and superior audio quality.

The device can drive up to 2 x 175 W into 4-Ω load

and 2 x 220 W into 3-Ω load and features a 2 VRMS

analog input interface that works seamlessly with high

performance DACs such as TI's PCM5242. In

addition to excellent audio performance, TPA3251

achieves both high power efficiency and very low

power stage idle losses below 1 W. This is achieved

through the use of 60 mΩ MOSFETs and an

optimized gate driver scheme that achieves

significantly lower idle losses than typical discrete

implementations.