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位置:TLV5614CPWR.A > TLV5614CPWR.A詳情

TLV5614CPWR.A中文資料

廠家型號

TLV5614CPWR.A

文件大小

687.21Kbytes

頁面數(shù)量

35

功能描述

2.7-V TO 5.5-V 12-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

TLV5614CPWR.A數(shù)據(jù)手冊規(guī)格書PDF詳情

Four 12-Bit D/A Converters

Programmable Settling Time of Either 3 μs

or 9 μs Typ

TMS320, (Q)SPI, and Microwire

Compatible Serial Interface

Internal Power-On Reset

Low Power Consumption:

8 mW, Slow Mode – 5-V Supply

3.6 mW, Slow Mode – 3-V Supply

Reference Input Buffer

Voltage Output Range . . . 2× the Reference

Input Voltage

Monotonic Over Temperature

Dual 2.7-V to 5.5-V Supply (Separate Digital

and Analog Supplies)

Hardware Power Down (10 nA)

Software Power Down (10 nA)

Simultaneous Update

applications

Battery Powered Test Instruments

Digital Offset and Gain Adjustment

Industrial Process Controls

Machine and Motion Control Devices

Communications

Arbitrary Waveform Generation

description

The TLV5614 is a quadruple 12-bit voltage output

digital-to-analog converter (DAC) with a flexible

4-wire serial interface. The 4-wire serial interface

allows glueless interface to TMS320, SPI, QSPI,

and Microwire serial ports. The TLV5614 is

programmed with a 16-bit serial word comprised

of a DAC address, individual DAC control bits, and

a 12-bit DAC value. The device has provision for

two supplies: one digital supply for the serial

interface (via pins DVDD and DGND), and one for

the DACs, reference buffers, and output buffers (via pins AVDD and AGND). Each supply is independent of the

other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the

DAC is controlled via a microprocessor operating on a 3 V supply (also used on pins DVDD and DGND), with

the DACs operating on a 5 V supply. Of course, the digital and analog supplies can be tied together.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB

output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode

makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to

allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits

within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD

terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow

DACs A and B to have a different reference voltage then DACs C and D.

The TLV5614 is implemented with a CMOS process and is available in a 16-terminal SOIC package. The

TLV5614C is characterized for operation from 0°C to 70°C. The TLV5614I is characterized for operation from

–40°C to 85°C.

更新時間:2025-9-12 10:32:00
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正品原裝--自家現(xiàn)貨-實(shí)單可談