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Choice of Memory Organizations

– SN74V263 – 8192 × 18/16384 × 9

– SN74V273 – 16384 × 18/32768 × 9

– SN74V283 – 32768 × 18/65536 × 9

– SN74V293 – 65536 × 18/131072 × 9

166-MHz Operation

6-ns Read/Write Cycle Time

User-Selectable Input and Output Port Bus

Sizing

– ×9 in to ×9 out

– ×9 in to ×18 out

– ×18 in to ×9 out

– ×18 in to ×18 out

Big-Endian/Little-Endian User-Selectable

Byte Representation

5-V-Tolerant Inputs

Fixed, Low First-Word Latency

Zero-Latency Retransmit

Master Reset Clears Entire FIFO

Partial Reset Clears Data, but Retains

Programmable Settings

Empty, Full, and Half-Full Flags Signal FIFO

Status

Programmable Almost-Empty and

Almost-Full Flags; Each Flag Can Default to

One of Eight Preselected Offsets

Selectable Synchronous/Asynchronous

Timing Modes for Almost-Empty and

Almost-Full Flags

Program Programmable Flags by Either

Serial or Parallel Means

Select Standard Timing (Using EF and FF

Flags) or First-Word Fall-Through (FWFT)

Timing (Using OR and IR Flags)

Output Enable Puts Data Outputs in

High-Impedance State

Easily Expandable in Depth and Width

Independent Read and Write Clocks Permit

Reading and Writing Simultaneously

High-Performance Submicron CMOS

Technology

Glueless Interface With ’C6x DSPs

Available in 80-Pin Thin Quad Flat Pack

(TQFP) and 100-Pin Ball Grid Array (BGA)

Packages

description

The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in

first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.

There is flexible ×9/×18 bus matching on both read and write ports.

The period required by the retransmit operation is fixed and short.

The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be

read, is fixed and short.

These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and

other applications that need to buffer large amounts of data and match buses of unequal sizes.

Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit

or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during

the master-reset cycle.

The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO

on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and

read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.

An output-enable (OE) input is provided for 3-state control of the outputs.