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Members of the Texas Instruments

SCOPE? Family of Testability Products

Members of the Texas Instruments

Widebus? Family

State-of-the-Art 3.3-V ABT Design Supports

Mixed-Mode Signal Operation (5-V Input

and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

UBT ? (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Bus Hold on Data Inputs Eliminates the

Need for External Pullup Resistors

B-Port Outputs of ’LVTH182502A Devices

Have Equivalent 25-Ω Series Resistors, So

No External Resistors Are Required

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

SCOPE? Instruction Set

? IEEE Standard 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

? Parallel-Signature Analysis at Inputs

? Pseudorandom Pattern Generation From

Outputs

? Sample Inputs/Toggle Outputs

? Binary Count From Outputs

? Device Identification

? Even-Parity Opcodes

Packaged in 64-Pin Plastic Thin Quad Flat

(PM) Packages Using 0.5-mm

Center-to-Center Spacings and 68-Pin

Ceramic Quad Flat (HV) Packages Using

25-mil Center-to-Center Spacings

description

The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members

of the Texas Instruments SCOPE? testability integrated-circuit family. This family of devices supports IEEE

Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to

the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the

capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and

D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes. Another use is as two

9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot

samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating

the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when

LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.

Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the

B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is

similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry

is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs

boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.