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Members of the Texas Instruments

WidebusE Family

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

Typical VOLP (Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

Ioff and Power-Up 3-State Support Hot

Insertion

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 500 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) VCC operation, but

with the capability to provide a TTL interface to a 5-V system environment.

Data flow from A to Y is controlled by the output-enable (OE) input. These devices operate in the transparent

mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high

or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock.

When OE is high, the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.