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位置:SN74LVCZ245ADWR.B > SN74LVCZ245ADWR.B詳情

SN74LVCZ245ADWR.B中文資料

廠家型號(hào)

SN74LVCZ245ADWR.B

文件大小

874.12Kbytes

頁(yè)面數(shù)量

21頁(yè)

功能描述

OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74LVCZ245ADWR.B數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

Operates From 2.7 V to 3.6 V

Inputs Accept Voltages to 5.5 V

Max tpd of 6.3 ns at 3.3 V

Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

Typical VOHV (Output VOH Undershoot)

>2 V at VCC = 3.3 V, TA = 25°C

Ioff and Power-Up 3-State Support Hot

Insertion

Supports Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V VCC)

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

description/ordering information

This octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation.

The SN74LVCZ245A is designed for asynchronous communication between data buses. The device transmits

data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are

effectively isolated.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator

in a mixed 3.3-V/5-V system environment.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry

disables the outputs, preventing damaging current backflow through the device when it is powered down. The

power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

更新時(shí)間:2025-9-22 10:23:00
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