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位置:SN74LVCH16T245DLR.B > SN74LVCH16T245DLR.B詳情

SN74LVCH16T245DLR.B中文資料

廠家型號

SN74LVCH16T245DLR.B

文件大小

645.97Kbytes

頁面數(shù)量

32

功能描述

SN74LVCH16T245 16-bit Dual-supply Bus Transceiver With Configurable Level-Shifting/Voltage Translation and Tri-State Outputs

數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74LVCH16T245DLR.B數(shù)據(jù)手冊規(guī)格書PDF詳情

1 Features

1? Control Inputs VIH/VIL Levels are Referenced to

V CCA Voltage

? VCC Isolation Feature – If Either VCC Input is at

GND, All Outputs are in the High-Impedance State

? Overvoltage-Tolerant Inputs and Outputs Allow

Mixed-Voltage-Mode Data Communications

? Fully Configurable Dual-Rail Design Allows Each

Port to Operate Over the Full 1.65 V to 5.5 V

Power-Supply Range

? Bus Hold on Data Inputs Eliminates the Need for

External Pullup and Pulldown Resistors

? Ioff Supports Partial-Power-Down Mode Operation

? Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

? ESD Protection Exceeds JESD 22

2 Applications

? Personal Electronics

? Industrial

? Enterprise

? Telecom

3 Description

This 16-bit noninverting bus transceiver uses two

separate configurable power-supply rails. The A port

is designed to track VCCA. VCCA accepts any supply

voltage from 1.65 V to 5.5 V. The B port is designed

to track VCCB. VCCB accepts any supply voltage from

1.65 V to 5.5 V. This allows for universal low-voltage

bidirectional translation between any of the 1.8-V,

2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVCH16T245 device control pins (1DIR,

2DIR, 1OE, and 2OE) are supplied by VCCA.

The SN74LVCH16T245 device is designed for

asynchronous communication between two data

buses. The logic levels of the direction-control (DIR)

input and the output-enable (OE) input activate either

the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The

device transmits data from the A bus to the B bus

when the B-port outputs are activated, and from the B

bus to the A bus when the A-port outputs are

activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW

level applied to prevent excess ICC and ICCZ.

更新時(shí)間:2025-9-20 15:01:00
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