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FEATURES

· Member of the Texas Instruments Widebus?

Family

· Operates From 1.65 V to 3.6 V

· Inputs Accept Voltages to 5.5 V

· Max tpd of 3.7 ns at 3.3 V

· Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

· Typical VOHV (Output VOH Undershoot)

>2 V at VCC = 3.3 V, TA = 25°C

· Ioff Supports Partial-Power-Down Mode

Operation

· Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage

With 3.3-V VCC)

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation and provides a high-performance bus

interface for wide data paths.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2)

input is high, all corresponding outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.