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FEATURES

· Operates From 1.65 V to 3.6 V

· Inputs Accept Voltages to 5.5 V

· Max tpd of 7.3 ns at 3.3 V

· Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

· Typical VOHV (Output VOH Undershoot)

>2 V at VCC = 3.3 V, TA = 25°C

· Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With

3.3-V VCC)

· Ioff Supports Partial-Power-Down Mode

Operation

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

DESCRIPTION/ORDERING INFORMATION

This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports,

bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the

device provides true data at the Q outputs.

A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.