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1 Features

? ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

? Qualified from –40°C to +125°C

? Supports 5-V VCC Operation

? Inputs Are Over Voltage Tolerant up to 5.5 V

? Supports Down Translation to VCC

? Maximum tpd of 4 ns at 3.3 V and 15-pF load

? Low Power Consumption, 10-μA Maximum ICC At

85°C

? ±24-mA Output Drive at 3.3 V

? Ioff Supports Partial-Power-Down Mode, and Back-

Drive Protection

? Available in the Texas Instruments

NanoFree? Package

? Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

2 Applications

? Wireless Headsets

? Motor Drives and Controls

? TVs

? Set-Top Boxes

? Audio

3 Description

The SN74LVC1G86 device performs the Boolean

function Y = AB + AB in positive logic. This single 2-

input exclusive-OR gate is designed for 1.65-V to 5.5-

V VCC operation.

If the input is low, the other input is reproduced in

true form at the output. If the input is high, the signal

on the other input is reproduced inverted at the

output. This device has low power consumption with

maximum tpd of 4 ns at 3.3 V and 15-pF capacitive

load. The maximum output drive is ±32-mA at 4.5 V

and ±24-mA at 3.3 V.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables the

outputs, preventing damaging current back flow

through the device when it is powered down.