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1FEATURES

? Inputs Are TTL-Voltage Compatible

? 4.5-V to 5.5-V VCC Operation

? Typical tpd of 4.9 ns at 5 V

? Typical V OLP (Output Ground Bounce) <0.8 V

at V CC = 5 V, TA = 25°C

? Typical V OHV (Output VOH Undershoot) >2.3 V

at VCC = 5 V, TA = 25°C

? Support Mixed-Mode Voltage Operation on All

Ports

? Ioff Supports Partial-Power-Down Mode

Operation

? Latch-Up Performance Exceeds 250 mA Per

JESD 17

? ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION

The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed

specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for

implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)

inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines

without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.