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1FEATURES

? Qualified for Automotive Applications

? 2-V to 5.5-V VCC Operation

? Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

? Typical VOHV (Output VOH Undershoot)

>2.3 V at VCC = 3.3 V, TA = 25°C

? Support Mixed-Mode Voltage Operation on All

Ports

? Ioff Supports Partial-Power-Down Mode

Operation

DESCRIPTION

The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.

This device features independent line drivers with 3-state outputs. Each output is disabled when the associated

output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the

outputs, preventing damaging current backflow through the devices when they are powered down.