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位置:SN74HC74MPWREP.A > SN74HC74MPWREP.A詳情

SN74HC74MPWREP.A中文資料

廠家型號(hào)

SN74HC74MPWREP.A

文件大小

432.48Kbytes

頁(yè)面數(shù)量

13頁(yè)

功能描述

DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74HC74MPWREP.A數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

1FEATURES

· Controlled Baseline

– One Assembly Site

– One Test Site

– One Fabrication Site

· Extended Temperature Performance of –55°C

to 125°C

· Enhanced Diminishing Manufacturing Sources

(DMS) Support

· Enhanced Product-Change Notification

· Qualification Pedigree (1)

· Wide Operating Voltage Range of 2 V to 6 V

· Outputs Can Drive up to 10 LSTTL Loads

· Low Power Consumption, 80 mA Max ICC

· Typical tpd = 15 ns

· ±4 mA Output Drive at 5 V

· Low Input Current of 1 mA Max

DESCRIPTION/ORDERING INFORMATION

The SN74HC74 device contains two independent D-type positive edge triggered flip-flops. A low level at the

preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When

PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred

to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and

is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed

without affecting the levels at the outputs.

更新時(shí)間:2025-9-21 16:00:00
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