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SN74GTLPH16912GR.B中文資料
SN74GTLPH16912GR.B數(shù)據(jù)手冊規(guī)格書PDF詳情
FEATURES
· Member of the Texas Instruments Widebus?
Family
· UBT? Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, and
Clock-Enabled Modes
· TI-OPC? Circuitry Limits Ringing on
Unevenly Loaded Backplanes
· OEC? Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
· Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
· LVTTL Interfaces Are 5-V Tolerant
· Medium-Drive GTLP Outputs (50 mA)
· LVTTL Outputs (–24 mA/24 mA)
· GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
· Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
· Bus Hold on A-Port Data Inputs
· Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
· Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
· ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The SN74GTLPH16912 is a medium-drive, 18-bit UBT? transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of
data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a
backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL)
backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels,
improved differential input, OEC? circuitry, and TI-OPC? circuitry. Improved GTLP OEC and TI-OPC circuits
minimize bus-settling time and have been designed and tested using several backplane models. The medium
drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 W.
GTLP is the Texas Instruments (TI?) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin
GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP
(VTT = 1.5 V and VREF = 1 V) signal levels.
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
TEXAS |
23+ |
TSSOP56 |
5000 |
原裝正品,假一罰十 |
|||
TEXAS |
17+ |
TSSOP |
6200 |
100%原裝正品現(xiàn)貨 |
|||
TEXAS |
23+ |
TSSOP |
66115 |
公司原裝現(xiàn)貨!主營品牌!可含稅歡迎查詢 |
|||
TI |
16+ |
TSSOP-56 |
8000 |
原裝現(xiàn)貨請來電咨詢 |
|||
TI |
24+ |
TSSOP-56 |
90000 |
一級代理商進口原裝現(xiàn)貨、假一罰十價格合理 |
|||
TI |
25+ |
TVSOP56 |
1407 |
百分百原裝正品 真實公司現(xiàn)貨庫存 本公司只做原裝 可 |
|||
TI |
24+ |
TVSOP56 |
1407 |
||||
TI |
20+ |
14 |
53650 |
TI原裝主營-可開原型號增稅票 |
|||
Texas Instruments |
24+ |
56-TVSOP |
65300 |
一級代理/放心采購 |
|||
TI/德州儀器 |
2447 |
14 |
100500 |
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨 |
SN74GTLPH16912GR.B 資料下載更多...
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