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Member of the Texas Instruments

Widebus? Family

TI-OPC? Circuitry Limits Ringing on

Unevenly Loaded Backplanes

OEC? Circuitry Improves Signal Integrity

and Reduces Electromagnetic Interference

Bidirectional Interface Between GTLP

Signal Levels and LVTTL Logic Levels

Split LVTTL Port Provides a Feedback Path

for Control and Diagnostics Monitoring

LVTTL Interfaces Are 5-V Tolerant

High-Drive GTLP Open-Drain Outputs

(100 mA)

LVTTL Outputs (?24 mA/24 mA)

Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for

Optimal Data-Transfer Rate and Signal

Integrity in Distributed Loads

Ioff, Power-Up 3-State, and BIAS VCC

Support Live Insertion

Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

? 2000-V Human-Body Model (A114-A)

? 1000-V Charged-Device Model (C101)

description

The SN74GTLP2033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted

LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and

flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback

path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides

a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal

levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result

of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC?

circuitry, and TI-OPC? circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have

been designed and tested using several backplane models. The high drive allows incident-wave switching in

heavily loaded backplanes with equivalent load impedance down to 11 Ω.