国产精品久久久久无码av色戒,大帝av在线一区二区三区,国产肥熟女视频一区二区三区,大陆少妇xxxx做受,被黑人猛躁10次高潮视频

? Contains Six Flip-Flops With Single-Rail

Outputs

? Buffered Clock and Direct Clear Inputs

? Applications Include:

Buffer/Storage Registers

Shift Registers

Pattern Generators

? Fully Buffered Outputs for Maximum

Isolation From External Disturbances

? Package Options Include Plastic

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a

direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred

to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level

and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either

the high or low level, the D-input signal has no effect at the output.

The SN74F174A is characterized for operation from 0°C to 70°C.