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位置:SN74CBT3306CPWR1G4.B > SN74CBT3306CPWR1G4.B詳情

SN74CBT3306CPWR1G4.B中文資料

廠家型號(hào)

SN74CBT3306CPWR1G4.B

文件大小

729.28Kbytes

頁(yè)面數(shù)量

18頁(yè)

功能描述

DUAL FET BUS SWITCH 5-V BUS SWITCH WITH -2-V UNDERSHOOT PROTECTION

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74CBT3306CPWR1G4.B數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

Undershoot Protection for Off-Isolation on

A and B Ports Up To ?2 V

Bidirectional Data Flow, With Near-Zero

Propagation Delay

Low ON-State Resistance (ron)

Characteristics (ron = 3 Ω Typical)

Low Input/Output Capacitance Minimizes

Loading and Signal Distortion

(Cio(OFF) = 5 pF Typical)

Data and Control Inputs Provide

Undershoot Clamp Diodes

Low Power Consumption

(ICC = 3 μA Max)

VCC Operating Range From 4 V to 5.5 V

Data I/Os Support 0 to 5-V Signaling Levels

(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)

Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

Ioff Supports Partial-Power-Down Mode

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Performance Tested Per JESD 22

? 2000-V Human-Body Model

(A114-B, Class II)

? 1000-V Charged-Device Model (C101)

Supports Both Digital and Analog

Applications: USB Interface, Bus Isolation,

Low-Distortion Signal Gating

description/ordering information

The SN74CBT3306C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),

allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the

SN74CBT3306C provides protection for undershoot up to ?2 V by sensing an undershoot event and ensuring

that the switch remains in the proper OFF state.

The SN74CBT3306C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs.

It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus

switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When

OE is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B

ports.

更新時(shí)間:2025-9-17 17:44:00
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