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位置:SN74AUC245RGYR.B > SN74AUC245RGYR.B詳情

SN74AUC245RGYR.B中文資料

廠家型號

SN74AUC245RGYR.B

文件大小

912.03Kbytes

頁面數(shù)量

14

功能描述

OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74AUC245RGYR.B數(shù)據(jù)手冊規(guī)格書PDF詳情

FEATURES

· Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

· Ioff Supports Partial-Power-Down Mode

Operation

· Sub-1-V Operable

· Max tpd of 1.7 ns at 1.8 V

· Low Power Consumption, 20-mA Max ICC

· ±8-mA Output Drive at 1.8 V

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This octal bus transceiver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V

VCC operation.

The SN74AUC245 is designed for asynchronous communication between data buses. The device transmits data

from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control

(DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

更新時(shí)間:2025-9-22 8:33:00
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