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FEATURES

· Member of the Texas Instruments Widebus?

Family

· EPIC? (Enhanced-Performance Implanted

CMOS) Submicron Process

· Output Ports Have Equivalent 26-W Series

Resistors, So No External Resistors Are

Required

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

DESCRIPTION

This 20-bit bus-interface D-type latch is designed for

1.65-V to 3.6-V VCC operation.

The SN74ALVCH162841 features 3-state outputs

designed specifically for driving highly capacitive or

relatively low-impedance loads. This device is

particularly suitable for implementing buffer registers,

unidirectional bus drivers, and working registers.

The SN74ALVCH162841 can be used as two 10-bit

latches or one 20-bit latch. The 20-bit latch is a

transparent D-type latch. The device has noninverting

data (D) inputs and provides true data at its outputs.

While the latch-enable (1LE or 2LE) input is high, the

Q outputs of the corresponding 10-bit latch follow the

D inputs. When LE is taken low, the Q outputs are

latched at the levels set up at the D inputs.

A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch

in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state,

the outputs neither load nor drive the bus lines significantly.

OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot and

undershoot.