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位置:SN74ALVCH162721DLR.B > SN74ALVCH162721DLR.B詳情

SN74ALVCH162721DLR.B中文資料

廠家型號(hào)

SN74ALVCH162721DLR.B

文件大小

862.86Kbytes

頁面數(shù)量

16

功能描述

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74ALVCH162721DLR.B數(shù)據(jù)手冊(cè)規(guī)格書PDF詳情

FEATURES

· Member of the Texas Instruments Widebus?

Family

· EPIC? (Enhanced-Performance Implanted

CMOS) Submicron Process

· Output Ports Have Equivalent 26-W Series

Resistors, So No External Resistors Are

Required

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

NOTE: For tape-and-reel order entry, the DGGR package is

abbreviated to GR.

DESCRIPTION

This 20-bit flip-flop is designed for low-voltage 1.65-V

to 3.6-V VCC operation.

The 20 flip-flops of the SN74ALVCH162721 are

edge-triggered D-type flip-flops with qualified clock

storage. On the positive transition of the clock (CLK)

input, the device provides true data at the Q outputs if

the clock-enable (CLKEN) input is low. If CLKEN is

high, no data is stored.

A buffered output-enable (OE) input places the 20

outputs in either a normal logic state (high or low

level) or the high-impedance state. In the

high-impedance state, the outputs neither load nor

drive the bus lines significantly. The high-impedance

state and increased drive provide the capability to drive bus lines without interface or pullup components. OE

does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot and

undershoot.

The SN74ALVCH162721 is characterized for operation from -40°C to 85°C.

更新時(shí)間:2025-9-23 16:01:00
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