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Bus Transceivers/Registers

Independent Registers and Enables for A

and B Buses

Multiplexed Real-Time and Stored Data

Choice of True or Inverting Data Paths

Choice of 3-State or Open-Collector

Outputs to A Bus

description

These devices consist of bus-transceiver circuits,

D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the

data bus or from the internal storage registers.

Output-enable (OEAB and OEBA) inputs are

provided to control the transceiver functions.

Select-control (SAB and SBA) inputs are provided

to select real-time or stored data transfer. The

circuitry used for select control eliminates the

typical decoding glitch that occurs in a multiplexer

during the transition between stored and real-time

data. A low input level selects real-time data, and

a high input level selects stored data. Figure 1

illustrates the four fundamental bus-management

functions that can be performed with the octal bus

transceivers and registers

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at

the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When

SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type

flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.

When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains

at its last state.

The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the

recommended maximum IOL for the -1 versions is increased to 48 mA. There are no -1 versions of the

SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.