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Controlled Baseline

– One Assembly/Test Site, One Fabrication

Site

Extended Temperature Performance of

–55°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product-Change Notification

Qualification Pedigree?

EPIC (Enhanced-Performance Implanted

CMOS) Process

Operating Range 2-V to 5.5-V VCC

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 1000 V Per

MIL-STD-833, Method 3015; Exceeds 150 V

Using Machine Model (C = 200 pF, R = 0)

description/ordering information

The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each

output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate

passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.