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位置:SN74ABT841ADWR.B > SN74ABT841ADWR.B詳情

SN74ABT841ADWR.B中文資料

廠家型號(hào)

SN74ABT841ADWR.B

文件大小

497.69Kbytes

頁(yè)面數(shù)量

19頁(yè)

功能描述

10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74ABT841ADWR.B數(shù)據(jù)手冊(cè)規(guī)格書(shū)PDF詳情

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

High-Impedance State During Power Up

and Power Down

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Package, and Plastic (NT)

and Ceramic (JT) DIPs

description

The SN54ABT841 and SN74ABT841A 10-bit

latches are designed specifically for driving highly

capacitive or relatively low-impedance loads.

They are particularly suitable for implementing

buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

The ten transparent D-type latches provide true

data at their outputs.

A buffered output-enable (OE) input can be used

to place the ten outputs in either a normal logic

state (high or low logic levels) or a

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines without need for interface or pullup

components.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT841 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT841A is characterized for operation from –40°C to 85°C.

更新時(shí)間:2025-9-21 10:03:00
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