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位置:SN74ABT533APWR.B > SN74ABT533APWR.B詳情

SN74ABT533APWR.B中文資料

廠家型號(hào)

SN74ABT533APWR.B

文件大小

999.4Kbytes

頁(yè)面數(shù)量

18頁(yè)

功能描述

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

生產(chǎn)廠商

TI2

SN74ABT533APWR.B數(shù)據(jù)手冊(cè)規(guī)格書(shū)PDF詳情

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Plastic (N) and Ceramic (J) DIPs, and

Ceramic Flat (W) Package

description

These octal transparent D-type latches with

3-state outputs are designed specifically for

driving highly capacitive or relatively

low-impedance loads. They are particularly

suitable for implementing buffer registers, I/O

ports, bidirectional bus drivers, and working

registers.

When the latch-enable (LE) input is high, the

Q outputs follow the complements of the data

(D) inputs. When LE is taken low, the Q outputs

are latched at the inverse of the levels at the

D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without need for interface or pullup components.

OE does not affect the internal operations of the latches. Previously stored data can be retained or new data

can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT533 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT533A is characterized for operation from –40°C to 85°C.

更新時(shí)間:2025-9-21 15:30:00
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