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Members of the Texas Instruments

WidebusE Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce)

< 0.8 V at VCC = 5 V, TA = 25°C

High-Impedance State During Power Up

and Power Down

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) Package and

380-mil Fine-Pitch Ceramic Flat (WD)

Package Using 25-mil Center-to-Center

Spacings

description

These 20-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. They are

particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The ’ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide

true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding

10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D

inputs.

A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch

in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,

the outputs neither load nor drive the bus lines significantly.

The output-enable input does not affect the internal operation of the latches. Old data can be retained or new

data can be entered while the outputs are in the high-impedance state.